A time-to-digital converter (TDC) translates a time difference between two input timing signals into a digital output bus. Depending on architecture, a TDC may function as a phase detector, a frequency detector, or both. A TDC monitors two digital timing signals and decides which timing signal arrived first. A TDC optionally monitors two timing signals to determine and digitally encode the time difference between the timing signals. A TDC also produces an output signal or bus of signals that encodes the time difference of which timing signal arrived first.
Symmetrical TDCs can be used for phase locked loops (PLLs) that demand zero static phase offset and low supply noise jitter. Linear TDCs are used for PLLs that demand low jitter performance. Known TDCs are not symmetric or linear at the same time resulting in jitter on the output clock provided by the PLLs.